STATE MACHINE FOR A PULSE OUTPUT FUNCTION

At least one exemplary embodiment comprises a system comprising an arithmetic logic unit; a memory comprising a pre-computed table of target pulse widths, changes in pulse width, and pulse counts distributed according to a constrained semi-logarithmic distribution, the memory connected to the arithmetic logic unit via a pipeline mechanism; and a state machine adapted to load each of the target pulse widths and changes in pulse width from the memory into the arithmetic logic unit at pre-determined intervals of pulse count while maintaining control of a pulse width generated by the arithmetic logic unit.