SYNTHESIS OF VERIFICATION LANGUAGES

Patent №

US 6,907,599

Granted

2005-06-14

Filed 2001

Owner

VERISITY LTD.

+1 more

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09880888

A method for synthesizing a verification language, and thereby enabling the verification language to be compiled into a target language. This method enables the underlying control structure of the verification language to be determined, and then used to map the dynamic behavior of the verification language onto the target language as part of a static framework. The process of synthesizing any type of verification language causes at least a portion of the implicit control structure of the software program to be constructed into the compiled output code, such that an additional scheduler or other type of runtime system may not be required. Therefore, the compiled output code should have a greater execution speed and should be operated more efficiently than the software programs which are written in the verification language itself.

AI hardwareG06F 30/3323G06F 8/51

AI classification

AI hardware1.00
Knowledge representation0.38
Natural language0.27
Machine learning0.03
Planning0.01
Vision0.00
Evolutionary computation0.00
Speech0.00

Ownership

VERISITY LTD.

assignment · 119080262

CADENCE DESIGN (ISRAEL) II LTD.

namechg · 172510976

Assignors

KASHAI, YARON, MORLEY, MATTHEW JOHN

On an employer assignment, the assignors are typically the inventors.

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