PROCESSOR AND INSTRUCTION EXECUTION METHOD WITH REDUCED ADDRESS INFORMATION

A processor includes a memory unit in which instructions having their constituent bytes stored in ascending address order alternate with instructions having their constituent bytes stored in descending address order. A single address pointer is used to read one instruction by reading up, and another instruction by reading down. The amount of address information needed for program execution is thereby reduced, as one address pointer suffices for two instructions. The address pointer may be provided by a branch instruction that also indicates whether to read up or down. An up-counter and a down-counter may be provided as address counters, enabling the two instructions to be read and executed concurrently. Four address counters may be provided, enabling a branch instruction to designate the execution of from one to four consecutive instructions.