MICROPROCESSOR HAVING A LOW-POWER CACHE MEMORY

A cache is provided which has low power dissipation. An execution engine generates a sequential fetch signal indicating that data required at a next cycle is stored at a next location of just previously used data. A line reuse buffer is provided which stores data that is stored in a data memory of the cache and is in the same cache line as data just previously used by the execution engine. In the case where the sequential fetch signal is received and data required according to a memory request signal is stored in the same cache line of the data memory as the just previously used data, a cache controller fetches data from the line reuse buffer and controls the cache so as to stay in a stand-by mode.