LEAKAGE CURRENT REDUCTION IN STANDARD CELLS

A method for reducing leakage currents in integrated circuits and the integrated circuits with reduced leakage currents that result from this method are disclosed. The present invention determines which transistors in a standard logic cell (also known as a standard cell) are not critical with respect to the ultimate speed of operation of the standard logic cell. After determining which transistors do not critically impact the speed of the standard logic cell's operation, these designated transistors are designed with either lengthened channels or their channels are implanted. Both circuit design techniques will increase the threshold voltage (VT) of the transistors and thereby reduce their leakage current. Standard cells with high VT transistors in their non-critical circuit pathways exhibit reduced leakage currents when compared with known logic cells.