METHOD AND SYSTEM FOR DESIGN VERIFICATION USING PROOF-PARTITIONING

Patent №

US 6,944,838

Granted

2005-09-13

Filed 2003

Owner

CADENCE DESIGN SYSTEMS, INC.

Lab

AI components

4

kr · planning · evo · hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10357657

A design verifier includes a bounded model checker, a proof partitioner and a fixed-point detector. The bounded model checker verifies a property to a depth K and either finds a counterexample, or generates a proof in the form of a directed acyclic graph. If a counterexample is found, the bounded model checker selectively increases K and verifies the property to the new larger depth using the original constraints. If no counterexample is found, the proof partitioner provides an over-approximation of the states reachable in one or more steps using a proof generated by the bounded model checker. The fixed-point detector detects whether the over-approximation is at a fixed point. If the over-approximation is at a fixed-point, the design is verified. If the over-approximation is not at a fixed point, the bounded model checker can iteratively use over-approximations as a constraint and verify the property to a depth K.

AI classification

Planning1.00
AI hardware0.93
Knowledge representation0.84
Evolutionary computation0.66
Vision0.19
Natural language0.00
Machine learning0.00
Speech0.00

Ownership

CADENCE DESIGN SYSTEMS, INC.

assignment · 137330378

Assignors

MCMILLAN, KENNETH L.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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