SYSTEM AND METHOD FOR SYNCHRONIZING A PLURALITY OF PROCESSORS IN A PROCESSOR ARRAY

A system and method is disclosed for synchronizing a plurality of processors in a processor array. The system and method synchronizes data communications between the processors by regulating memory access of the processors to memory bytes of an asynchronous variable memory. Each memory byte in the asynchronous variable memory is a “read full and write empty” memory byte. Except for a system processor, each processor in the process array can only write data to an empty memory byte and can only read data from a full memory byte. The processors are prevented from untimely overwriting data and from untimely reading data. This keeps the data communications between the processors properly synchronized.