FAULT TOLERANT OPERATION OF FIELD PROGRAMMABLE GATE ARRAYS

A method of fault tolerant operation of field programmable gate arrays (FPGAs), whether as an embedded portion of a system-on-chip or other application specific integrated circuit, utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into a self-testing area and a working area. Within the self-testing area, programmable interconnect resources of the FPGA are tested for faults. Upon the detection of one or more faults within the interconnect resources, the faulty interconnect resources are identified and a determination is made whether utilization of the faulty interconnect resources is compatible with an intended operation of the FPGAs. If the faulty interconnect resources are compatible with the intended operation of the FPGA, utilization of the faulty interconnect resource is allowed to provide fault tolerant operation of the FPGA. If the faulty interconnect resources are not compatible with the intended operation of the FPGA, on the other hand, a multi-step reconfiguration process may be initiated which attempts to minimize the effects of each reconfiguration on the overall performance of the FPGA. In an alternate embodiment, the entire FPGA may be configured as one or more self-testing areas during off-line testing, such as manufacturing testing.