ARCHITECTURES FOR DISCRETE WAVELET TRANSFORMS

A microprocessor structure for performing a discrete wavelet transform operation, said discrete wavelet transform operation comprising decomposition of an input signal comprising a vector of r×km input samples, r, k and m being non-zero positive integers, over a specified number of decomposition levels j, where j is an integer in the range 1 to J, starting from a first decomposition level and progressing to a final decomposition level, said microprocessor structure having a number of processing stages, each of said number of processing stages corresponding to a decomposition level j of the discrete wavelet transform operation and being implemented by a number of basic processing elements, the number of basic processing elements implemented in each of said processing stages decreasing by a factor of k from a decomposition level j to a decomposition level j+1.