SHARED BUFFER TYPE VARIABLE LENGTH PACKET SWITCH

Patent №

US 6,977,941

Granted

2005-12-20

Filed 2001

Owner

HITACHI, LTD.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

09791791

A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.

AI hardwareH04L 49/103H04L 49/3018H04L 49/3027H04L 49/351H04L 49/40

AI classification

AI hardware0.87
Knowledge representation0.01
Machine learning0.01
Natural language0.00
Speech0.00
Evolutionary computation0.00
Vision0.00
Planning0.00

Ownership

HITACHI, LTD.

assignment · 115650487

Assignors

TAKAHASHI, MASAMI, MAKIMOTO, AKIO, KOZAKI, TAKAHIKO, KANNO, TETAYUKI, OGINUMA, YASUO, NAKAYAMA, KAORI, WADE, MITSUHIRO, MORIWAKI, NORIHIKO, FUKANO, MASUMI, FUTAMI, YOSHO

On an employer assignment, the assignors are typically the inventors.

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