NAND FLASH MEMORY INTERFACE DEVICE

An interface device and method thereof interfacing between a host processor and a NAND flash memory includes a register file, an internal memory, a flash interface portion, and a finite state machine. The register file receive a command from the host processor to control an operation of the NAND flash memory and an operation information to execute the command and storing the command and the operation information. The flash interface portion controls a control signal to operate the NAND flash memory, outputs the command, the operation information, or the host data, and controls an I/O signal wire through which the flash data is inputted to the NAND flash memory. The finite state machine extracts the command and the operation information from the register file and controls the internal memory and the flash interface portion to execute the command.