Patent №
US 6,993,753
Granted
2006-01-31
Filed 2001
Owner
FUJITSU LIMITED
Lab
—
AI components
3
ml · nlp · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09774685
The object of the present invention is to provided a compiler for parallel computers that enable rapid processing by introducing a new data structure. A compiler 20 which compiles a source program 10, which includes a parallelization directive, executes a step of detecting a parallelization directive in the source program; and if the parallelization directive is detected, generating a front-end intermediate language for the parallelization directive by positioning on a storage region, each processing code of at least part of the parallelization directive with a hierarchical structure in accordance with an internal structure of the parallelization directive. In addition, the compiler 20 may execute a step of: adding to the front-end intermediate language of a statement to which the parallelization directive is applied, reference information from the front-end intermediate language of the statement to which the parallelization directive is applied, to the front-end intermediate language for the parallelization directive.
AI classification
Ownership
FUJITSU LIMITED
assignment · 115160202
Assignors
YAMANAKA, YUTAKA, ISHIKAWA, TAKAHIRO
On an employer assignment, the assignors are typically the inventors.