Patent №
US 7,032,076
Granted
2006-04-18
Filed 2002
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10244250
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.
AI classification
AI hardware0.85
Speech0.07
Knowledge representation0.03
Evolutionary computation0.02
Natural language0.01
Machine learning0.00
Vision0.00
Planning0.00
Ownership
INTEL CORPORATION
assignment · 134480856
Assignors
SPRANGLE, ERIC A., ROHILLAH, ANWAR Q.
On an employer assignment, the assignors are typically the inventors.
From the same owner
DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICYUS 12,693,977 · 2026RECOGNITION, REIDENTIFICATION AND SECURITY ENHANCEMENTS USING AUTONOMOUS MACHINESUS 12,694,657 · 2026DEPTH AND MOTION ESTIMATIONS IN MACHINE LEARNING ENVIRONMENTSUS 12,694,659 · 2026Apparatus, device, method and computer program for an autonomously acting machine or a computer systemUS 12,686,127 · 2026Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page MigrationUS 12,688,146 · 2026Generating Pretrained Sparse Student Model for Transfer LearningUS 12,688,422 · 2026OUT-OF-DISTRIBUTION DETECTION USING A NEURAL NETWORKUS 12,688,676 · 2026METHODS AND APPARATUS TO DETECT A REGION OF INTEREST BASED ON VARIABLE RATE SHADINGUS 12,689,741 · 2026