BUS ARBITER FOR INTEGRATED CIRCUIT SYSTEMS

Systems and methods for bus arbitration in an integrated circuit system, which prevent discrepancies of bus occupation rates (or the number of bus occupancies) and which provide programmable bus occupation rates for bus masters. In one aspect, a bus arbiter for an integrated circuit system including a plurality of bus masters, comprises a program file comprising a plurality of program registers, wherein each program register is associated with one of the bus masters and stores a predetermined value of a bus occupation rate assigned to the bus master, a temporary file comprising a plurality of temporary registers, wherein each temporary register is associated with one of the bus masters and stores a current value of the bus occupation rate of the bus master, and a point register that designates the bus master having the highest priority among the bus masters at a given time.