Patent №
US 7,054,988
Granted
2006-05-30
Filed 2003
Owner
LSI LOGIC CORPORATION
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10418236
The present invention may generally provide a processor circuit comprising a processor, a first bus, a bus pipeline stage, and a second bus. The first bus may be coupled to the processor. The bus pipeline stage may be coupled between the first bus and the second bus and configured to delay an access between the first bus and the second bus at least one pipeline cycle.
PlanningG06F 13/4054
AI classification
Planning0.96
Evolutionary computation0.00
Natural language0.00
AI hardware0.00
Machine learning0.00
Knowledge representation0.00
Speech0.00
Vision0.00
Ownership
LSI LOGIC CORPORATION
assignment · 139870685
Assignors
HILS, ANDREAS
On an employer assignment, the assignors are typically the inventors.
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