Patent №
US 7,058,636
Granted
2006-06-06
Filed 2001
Owner
PAONESSA RESEARCH, LIMITED LIABILITY COMPANY
Lab
—
AI components
2
kr · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09755286
Computer systems are typically designed with multiple levels of memory hierarchy. Prefetching has been employed to overcome the latency of fetching data or instructions from or to memory. In modern transaction processing systems, database servers, operating systems, and other commercial and engineering applications, information is frequently organized in trees, graphs, and linked lists. Lack of spatial locality results in a high probability that a miss will be incurred at each cache in the memory hierarchy. The present invention significantly increases the cache hit rates of many important data structure traversals, and thereby the potential throughput of the computer system and application in which it is employed. For data structure traversals in which the traversal path may be predetermined, a transformation is performed on the data structure that permits references to nodes that will be traversed in the future be computed sufficiently far in advance to prefetch the data into cache.
AI classification
Ownership
PAONESSA RESEARCH, LIMITED LIABILITY COMPANY
assignment · 188750104