DATA PACKET SWITCHING NODE ACCOMMODATING VERY HIGH BIT RATE INTERFACES

A data packet switching node, for use in an asynchronous digital network, that has an input stage that cuts data packets into segments of constant length, a switching matrix having input ports and output ports supporting identical bit rates B switching the segments and an output stage reconstructing the data packets from the segments supplied by the output ports of said switching matrix. The input stage has at least one input interface with a bit rate equal to a multiple of B, ki*B, and splits the data packet into ki input ports of the switching matrix. The output stage has at least one output interface with a bit rate equal to a multiple of B, ko*B, and reconstructs a data packet with a bit rate equal to ko*B by concatenating segments supplied by ko output ports of the switching matrix where ki*ko>1.