Patent №
US 7,100,129
Granted
2006-08-29
Filed 2003
Owner
CADENCE DESIGN SYSTEMS, INC.
Lab
—
AI components
2
ml · planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10342862
A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangle.
AI classification
Planning0.95
Machine learning0.68
Evolutionary computation0.43
AI hardware0.13
Knowledge representation0.07
Natural language0.01
Speech0.00
Vision0.00
Ownership
CADENCE DESIGN SYSTEMS, INC.
assignment · 136880351
Assignors
SALOWE, JEFFREY S., NEQUIST, ERIC
On an employer assignment, the assignors are typically the inventors.
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