Patent №
US 7,111,176
Granted
2006-09-19
Filed 2000
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09538954
The present invention is a method and apparatus to generates an isolated bus cycle for a transaction in a processor. A configuration storage contains configuration parameters to configure a processor in one of a normal execution mode and an isolated execution mode. An access generator circuit generates an isolated access signal using at least one of the isolated area parameters and access information in the transaction. The isolated access signal is asserted when the processor is configured in the isolated execution mode. A bus cycle decoder generates an isolated bus cycle corresponding to a destination in the transaction using the asserted isolated access signal and the access information.
AI classification
Ownership
INTEL CORPORATION
assignment · 110150571
Assignors
ELLISON, CARL M., GOLLIVER, ROGER A., HERBERT, HOWARD C., LIN, DERRICK C., MCKEEN, FRANCIS X., NEIGER, GIL, RENERIS, KEN, SUTTON, JAMES A.
On an employer assignment, the assignors are typically the inventors.