METHOD AND APPARATUS FOR PIPELINING ORDERED INPUT/OUTPUT TRANSACTIONS TO COHERENT MEMORY IN A DISTRIBUTED MEMORY, CACHE COHERENT, MULTI-PROCESSOR SYSTEM
Patent №
US 7,124,252
Granted
2006-10-17
Filed 2000
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
09643380
An approach for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system. A prefetch engine prefetches data from the distributed, coherent memory in response to a transaction from an input/output bus directed to the distributed, coherent memory. An input/output coherent cache buffer receives the prefetched data and is kept coherent with the distributed, coherent memory and with other caching agents in the system.
AI classification
Ownership
INTEL CORPORATION
assignment · 113740169
Assignors
KHARE, MANOJ, KUMAR, AKILESH, LOOI, LILY P., CRETA, KENNETH C.
On an employer assignment, the assignors are typically the inventors.