TARGETED FAULT TOLERANCE BY SPECIAL CPU INSTRUCTIONS

Patent №

US 7,146,530

Granted

2006-12-05

Filed 2003

Owner

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10623099

One embodiment disclosed relates to a microprocessor for targeted fault-tolerant computing. The microprocessor's decode circuitry is configured to decode a fault-tolerant version of an instruction and a non-fault-tolerant version of the instruction distinctly from each other. The microprocessor's execution circuitry is configured to execute the fault-tolerant version of the instruction with redundancy checking and to execute the non-fault-tolerant version of the instruction without redundancy checking.

AI hardwareG06F 11/1641G06F 9/30181

AI classification

AI hardware0.92
Natural language0.02
Evolutionary computation0.01
Knowledge representation0.00
Planning0.00
Speech0.00
Machine learning0.00
Vision0.00

Ownership

HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

assignment · 149670335

Assignors

POMARANSKI, KEN GARY, BARR, ANDREW HARVEY, SHIDLA, DALE JOHN

On an employer assignment, the assignors are typically the inventors.

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