METHOD OF FORMING AN INTEGRATED CIRCUIT HAVING NANOCLUSTER DEVICES AND NON-NANOCLUSTER DEVICES

Patent №

US 7,183,159

Granted

2007-02-27

Filed 2005

Owner

FREESCALE SEMICONDUCTOR, INC.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11035913

An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions. Formation of the gate oxides of the transistors is sequenced based upon the gate oxide thickness and function of the transistors. Thin gate oxides for at least one region of transistors are formed after the formation of gate oxides for the region including the transistors having the nanocluster layer.

AI hardwareH10B 41/49B82Y 10/00H10B 41/40H10D 84/0144H10D 84/038H10D 84/83H10D 30/62Y10S 438/962+2 more

AI classification

AI hardware0.53
Planning0.01
Machine learning0.01
Knowledge representation0.00
Natural language0.00
Vision0.00
Speech0.00
Evolutionary computation0.00

Ownership

FREESCALE SEMICONDUCTOR, INC.

assignment · 161800953

Assignors

RAO, RAJESH A., STEIMLE, ROBERT F.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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