PROGRAMMABLE LOGIC BLOCK HAVING IMPROVED PERFORMANCE WHEN FUNCTIONING IN SHIFT REGISTER MODE

A programmable logic block reduces output delay by bypassing a final slave latch when programmed to function as a shift register. The logic block includes memory cells, a multiplexer structure, and a bypass select multiplexer (BSM). The memory cells are coupled in series to form a shift register controlled by a shift clock, each bit including two paired memory cells implementing master and slave latches. Each memory cell drives an input terminal of the multiplexer structure. The BSM drives a select terminal of the multiplexer structure and selects one signal from each pair of the memory cells. The shift clock drives one data input terminal of the BSM. When in shift register mode, the shift clock simultaneously shifts a value in each master latch to the corresponding slave latch and selects a value from one of the master latches. The output path bypasses the slave latch of the selected bit.