Patent №
US 7,203,799
Granted
2007-04-10
Filed 2004
Owner
ALTERA CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10815559
Methods and apparatus are provided for handling events such as faults and resets. Specialized circuitry or hardware is provided within a processor to invalidate the cache line associated with the processor cache reset address. Based on the invalided state of the cache reset address line, the processor obtains new instructions from data memory. The new instructions can be configured to invalidate the remaining cache lines using software mechanisms.
AI hardwareG06F 12/0891
AI classification
AI hardware1.00
Evolutionary computation0.04
Natural language0.00
Knowledge representation0.00
Machine learning0.00
Vision0.00
Speech0.00
Planning0.00
Ownership
ALTERA CORPORATION
assignment · 150750885
Assignors
BALL, JAMES LORAN
On an employer assignment, the assignors are typically the inventors.
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