HARDWARE ACCELERATION OF DISPLAY DATA CLIPPING

Embodiments of the present invention are directed to a method and apparatus for hardware acceleration of display data clipping. In one embodiment, all display data is presented to the display system. The display system uses its hardware to clip the undesired data and display the desired data. In one embodiment, the display system has one or more clipping registers. As display data arrives from each source, the information's display location is classified by all the clipping registers. Only pixels which are calculated to be visible by the clipping registers is written to memory for later display. In one embodiment, the display system has an extra amount of memory, termed “display mask memory.” In one embodiment, there is a corresponding data location in the display mask memory for each pixel in the display memory. In one embodiment, the display system has another set of memory, termed “low-resolution display mask memory.” In yet another embodiment, the display data is presented to the display system from a server located away from the display system. The display data is presented via a network.