ENHANCED STRUCTURE OF EXTENSIBLE TIME-SHARING BUS CAPABLE OF REDUCING PIN NUMBER, EXTENDING MEMORY CAPACITY, AND PERFORMING I/O MAPPING ACCESS AND BLOCK ACCESS

An enhanced structure of extensible time-sharing bus, which essentially uses an address and data bus in time-sharing to send addresses and data between a microprocessor and a memory through a microprocessor interface and a memory interface, and a logic combination of two control lines to determine address transfer, data read or data write on the address and data bus, thereby reducing interface pins and obtaining flexible and multiplicative memory.