Patent №
US 7,296,140
Granted
2007-11-13
Filed 2006
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11331658
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.
AI classification
AI hardware0.91
Evolutionary computation0.04
Knowledge representation0.02
Speech0.00
Natural language0.00
Machine learning0.00
Planning0.00
Vision0.00
Ownership
INTEL CORPORATION
assignment · 174670097
Assignors
SPRANGLE, ERIC A., ROHILLAH, ANWAR Q.
On an employer assignment, the assignors are typically the inventors.
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