SOC-BASED CORE SCAN CHAIN LINKAGE SWITCH

Disclosed herein is an SoC-based core scan chain linkage switch. The core scan chain linkage switch includes test bus terminals, scan chain input/output terminals, a switch unit and SCLK, UCLK, Mode and Enable signals. The test bus terminals apply instructions and input/output test data. The scan chain input/output terminals link with the scan chains of an embedded core. The switch unit completes a linkage configuration between the test bus terminals and the scan chain input/output terminals in response to the applied instructions. The SCLK, UCLK and Mode signals apply the instructions to dynamically reconfigure the switch unit and update the linkage configuration of the switch unit, and the Enable signal activates and deactivates the switch unit.