MEMORY ORGANIZATION ALLOWING SINGLE CYCLE POINTER ADDRESSING WHERE THE ADDRESS OF THE POINTER IS ALSO CONTAINED IN ONE OF THE MEMORY LOCATIONS

Patent №

US 7,305,543

Granted

2007-12-04

Filed 2006

Owner

KONINKLIJKE PHILIPS ELECRONICS, N.V.

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10566514

All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers, a read access involves multiplexing out of appropriate data for the pointer address from these pointer registers to form a target pointer address. This target pointer address is then used as an address to access RAM without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM.

AI hardwareG06F 9/321G06F 9/3012G06F 9/3013G06F 9/3016G06F 9/35

AI classification

AI hardware1.00
Evolutionary computation0.04
Planning0.01
Natural language0.00
Knowledge representation0.00
Machine learning0.00
Vision0.00
Speech0.00

Ownership

KONINKLIJKE PHILIPS ELECRONICS, N.V.

assignment · 175290120

Assignors

GOODHUE, GREGORY, KAHAN, ATA, DING, ZHIMIN

On an employer assignment, the assignors are typically the inventors.

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