Patent №
US 7,334,178
Granted
2008-02-19
Filed 2005
Owner
XSIGO SYSTEMS
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11222590
Methods and apparatus are provided for verifying and validating operation of a design under test (DUT). Input data sequences having information used to check expected outputs are provided to a DUT. The input data sequences include checking headers and data. The checking headers and data are randomized using encryption to verify and validate operation of the DUT on a variety of bit sequences. Different keys are used to allow further scrambling.
AI classification
Ownership
XSIGO SYSTEMS
assignment · 198980657
Assignors
AULAGNIER, PIERRE
On an employer assignment, the assignors are typically the inventors.