IMPLEMENTING CHECK INSTRUCTIONS IN EACH THREAD WITHIN A REDUNDANT MULTITHREADING ENVIRONMENTS

Patent №

US 7,353,365

Granted

2008-04-01

Filed 2004

Owner

INTEL CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

10953887

A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.

AI hardwareG06F 11/1494G06F 11/1695

AI classification

AI hardware0.78
Evolutionary computation0.00
Vision0.00
Natural language0.00
Speech0.00
Machine learning0.00
Knowledge representation0.00
Planning0.00

Ownership

INTEL CORPORATION

assignment · 158490644

Assignors

MUKHERJEE, SHUBHENDU S., EMER, JOEL S., REINHARDT, STEVEN K., WEAVER, CHRISTOPHER T.

On an employer assignment, the assignors are typically the inventors.

From the same owner

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