SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT

Patent №

US 7,409,648

Granted

2008-08-05

Filed 2005

Owner

NEC ELECTRONICS CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11141329

The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores interconnection information in an interconnection information storage unit 104. An arithmetic operation unit 102 acquires the interconnection information upon accessing the interconnection information storage unit 104 and acquires an arithmetic operation parameter while accessing the arithmetic operation parameter storage unit 105 to determine a width W of the interconnection based on these values. That is, the width W of the interconnection is made to determine upon multiplying (current i)1/3 by the arithmetic operation parameter (constant), which current is caused to flow through the interconnection.

AI hardwareG06F 30/394H01L 23/528H10W 20/43H01L 2924/0002

AI classification

AI hardware0.73
Vision0.08
Natural language0.01
Speech0.00
Evolutionary computation0.00
Machine learning0.00
Knowledge representation0.00
Planning0.00

Ownership

NEC ELECTRONICS CORPORATION

assignment · 166600098

Assignors

YOKOGAWA, SHINJI

On an employer assignment, the assignors are typically the inventors.

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