COVERAGE CIRCUIT FOR PERFORMANCE COUNTER

A coverage circuit for use with a general purpose performance counter (“GPPC”) connected to a bus for capturing test coverage information encoded as N one-hot signals indicative of coverage in a logic design. An OR logic block is included for bit-wise ORing the N one-hot signals with a N-bit mask value stored in a register block so that an N-bit output may be generated by the OR logic block depending on the logic transitions of the one-hot signals. A Multiplexer (MUX) block is provided for selecting the N-bit output from the OR logic block under control of at least one control signal, wherein the N-bit output is operable to be stored into the register block when selected by the MUX block.