PROCESSOR AND PROGRAMMABLE LOGIC COMPUTING ARRANGEMENT

A computing arrangement including a processor and programmable logic. In various embodiments, the arrangement includes an instruction processing circuit coupled to a programmable logic circuit, and a memory arrangement coupled to the instruction processing circuit and to the programmable logic circuit. The instruction processing circuit executes instructions of a native instruction set, and the programmable logic is configured to dynamically translate input instructions to translated instructions of the native instruction set. The translated instructions are stored in a translation cache in the memory arrangement, and the translation cache is managed by the programmable logic. The programmable logic then provides the translated instructions to the instruction processing circuit for execution.