Patent №
US 7,444,565
Granted
2008-10-28
Filed 2004
Owner
ITT MANUFACTURING ENTERPRISES, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
10994476
A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output from each programmable logic component to a fixed logic component, examining the outputs, and determining a validated output from among the outputs. An architecture for mitigating logic upsets includes an input, a plurality of programmable logic components, and a fixed logic component. The input is provided to each of the programmable logic components. Each programmable logic components includes an encryption algorithm and a first majority voting logic, and processes the respective input to determine a respective output. The fixed logic component includes a second majority voting logic. The fixed logic component receives each respective output from the programmable logic components, examines the outputs, and determines a validated output.
AI classification
Ownership
ITT MANUFACTURING ENTERPRISES, INC.
assignment · 164870675
Assignors
HAIGHT, CHARLES F.
On an employer assignment, the assignors are typically the inventors.