TESTING EMBEDDED MEMORY IN AN INTEGRATED CIRCUIT

An integrated circuit includes a first bus and at least one array of embedded memories. Each array includes a second bus such as a bidirectional bus coupled to the embedded memories and to the first bus such that test vectors in the form of data words can be written from the first bus to selected embedded memories in the array. Also included is a built-in-self-test (BIST) circuit operable to compare data words on the first bus to data words read back from the selected embedded memories through the bidirectional bus.