Patent №
US 7,525,673
Granted
2009-04-28
Filed 2006
Owner
TOKYO ELECTRON, LTD.
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11484460
A system for examining a patterned structure formed on a semiconductor wafer using an optical metrology model includes a first fabrication cluster, a metrology cluster, an optical metrology model optimizer, and a real time profile estimator. The first fabrication cluster processes a wafer, the wafer having a first patterned and a first unpatterned structure. The metrology cluster measures diffraction signals off the first patterned and first unpatterned structure. The metrology model optimizer optimizes an optical metrology model of the first patterned structure. The real time profile estimator creates an output comprising underlying film thickness, critical dimension, and profile of the first patterned structure.
AI classification
Ownership
TOKYO ELECTRON, LTD.
assignment · 182740607
Assignors
VUONG, VI, BAO, JUNWEI
On an employer assignment, the assignors are typically the inventors.