METHOD AND SYSTEM FOR CHIP DESIGN USING PHYSICALLY APPROPRIATE COMPONENT MODELS AND EXTRACTION
Patent №
US 7,533,359
Granted
2009-05-12
Filed 2006
Owner
CADENCA DESIGN SYSTEMS, INC.
+1 more
Lab
—
AI components
1
planning
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11437583
An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for modeling transistors since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The expected geometric shape includes systematic variations, which can be determined based on the layout, and the expected random variations, which can be determined based on the lithographic process.
AI classification
Ownership
CADENCA DESIGN SYSTEMS, INC.
assignment · 180920475
CADENCE DESIGN SYSTEMS, INC.
correct · 192200224
Assignors
SCHEFFER, LOUIS K., PHILLIPS, JOEL R.
On an employer assignment, the assignors are typically the inventors.