Patent №
US 7,581,065
Granted
2009-08-25
Filed 2005
Owner
INTEL CORPORATION
Lab
—
AI components
2
evo · hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11101785
A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.
AI classification
AI hardware0.99
Evolutionary computation0.56
Knowledge representation0.23
Planning0.00
Vision0.00
Machine learning0.00
Natural language0.00
Speech0.00
Ownership
INTEL CORPORATION
assignment · 164640989
Assignors
O'CONNOR, DENNIS M., MORROW, MICHAEL W.
On an employer assignment, the assignors are typically the inventors.
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