Patent №
US 7,583,207
Granted
2009-09-01
Filed 2007
Owner
KABUSHIKI KAISHA TOSHIBA
+1 more
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11872387
A logic circuit that executes a prescribed arithmetic processing includes a decoder that converts one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of the input data, an interconnect network that is connected to the decoder, changes a bit pattern of the first plurality of bit data and generates a second plurality of bit data, according to receiving the first plurality of bit data converted according to the decoder, and substituting a bit position of the received first plurality of bit data for the purpose of the prescribed arithmetic operation, and an encoder connected to the interconnect network and converts the second plurality of bit data generated in the interconnect network into one or more binary output data.
AI classification
Ownership
KABUSHIKI KAISHA TOSHIBA
assignment · 203480166
AT&T WIRELESS SERVICES, INC.
assignment · 214570828
Assignors
AGRAWAL, ANURAAG
On an employer assignment, the assignors are typically the inventors.