Patent №
US 7,590,905
Granted
2009-09-15
Filed 2005
Owner
SYNTEST TECHNOLOGIES, INC.
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11122244
A pipelined scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit without reducing the speed of the scan chain operation in scan-test mode or self-test mode. The integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. A decompressor is embedded between N scan chains and M scan chains, where N<M, to broadcast compressed scan data patterns driven through the N scan chains into decompressed scan data patterns stored in the M scan chains. To speed up the shift-in/shift-out operation during decompression, the decompressor can be further split into two or more pipelined decompressors each placed between two sets of intermediate scan chains. The invention further comprises one or more pipelined compressors to speed up the shift-in/shift-out operation during compression.
AI classification
Ownership
SYNTEST TECHNOLOGIES, INC.
assignment · 168850073
Assignors
ABDEL-HAFEZ, KHADER S., WANG, LAUNG-TERN (L.-T.), SHEN, BORYAU (JACK), WU, SHIANLING
On an employer assignment, the assignors are typically the inventors.