EFFECTIVE CACHING MECHANISM WITH COMPARATOR COUPLED TO PROGRAMMABLE REGISTERS TO STORE PLURALITY OF THRESHOLDS IN ORDER TO DETERMINE WHEN TO THROTTLE MEMORY REQUESTS
Patent №
US 7,594,042
Granted
2009-09-22
Filed 2006
Owner
INTEL CORPORATION
Lab
—
AI components
1
hardware
Assignment
Recorded
Dataset
AIPD
2023_r1 edition
Application
11480669
A system includes a plurality of bus masters that generate direct memory access requests to access a protected memory device. Before granting the access, the system checks for memory protection information stored in a cache. The cache is shared by the bus masters and allocation of the cache entries is prioritized among the bus masters.
AI classification
AI hardware0.62
Planning0.08
Natural language0.00
Knowledge representation0.00
Machine learning0.00
Evolutionary computation0.00
Speech0.00
Vision0.00
Ownership
INTEL CORPORATION
assignment · 203430973
Assignors
LIM, SU WEI
On an employer assignment, the assignors are typically the inventors.
From the same owner
DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICYUS 12,693,977 · 2026RECOGNITION, REIDENTIFICATION AND SECURITY ENHANCEMENTS USING AUTONOMOUS MACHINESUS 12,694,657 · 2026DEPTH AND MOTION ESTIMATIONS IN MACHINE LEARNING ENVIRONMENTSUS 12,694,659 · 2026Apparatus, device, method and computer program for an autonomously acting machine or a computer systemUS 12,686,127 · 2026Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page MigrationUS 12,688,146 · 2026Generating Pretrained Sparse Student Model for Transfer LearningUS 12,688,422 · 2026OUT-OF-DISTRIBUTION DETECTION USING A NEURAL NETWORKUS 12,688,676 · 2026METHODS AND APPARATUS TO DETECT A REGION OF INTEREST BASED ON VARIABLE RATE SHADINGUS 12,689,741 · 2026