IMPLEMENTATION OF LDPC (LOW DENSITY PARITY CHECK) DECODER BY SWEEPING THROUGH SUB-MATRICES

Patent №

US 7,617,433

Granted

2009-11-10

Filed 2006

Owner

BROADCOM CORPORATION

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11360268

Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).

AI hardwareH03M 13/116H03M 13/1137H03M 13/255H03M 13/6566H03M 13/27H03M 13/6362

AI classification

AI hardware1.00
Knowledge representation0.08
Vision0.01
Natural language0.00
Machine learning0.00
Speech0.00
Evolutionary computation0.00
Planning0.00

Ownership

BROADCOM CORPORATION

assignment · 175800238

Assignors

LEE, TAK K., TRAN, HAU THIEN, SHEN, BA-ZHONG, CAMERON, KELLY BRIAN

On an employer assignment, the assignors are typically the inventors.

From the same owner

© 2026 NYSGPT2525 LLC