DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING FLOATING POINT MULTIPLICATION

Patent №

US 7,640,286

Granted

2009-12-29

Filed 2005

Owner

ARM LIMITED

Lab

AI components

1

hardware

Assignment

Recorded

Dataset

AIPD

2023_r1 edition

Application

11077358

A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors, and sum logic operable to perform a sum operation to add a first set of bits of each of the pair of 2n-bits vectors. Sticky determination logic is also provided for determining from a second set of bits of each of the pair of 2n-bit vectors a sticky value, and selector logic is then used to derive the n-bit result from the output of the sum logic with reference to the sticky value. The sticky determination logic comprises a half-adder structure operable to generate carry and sum vectors from a negated version of the second set of bits of each the pair of 2n-bit vectors, and combination logic for performing a logical XOR operation on the carry and sum vectors with the least significant carry bit set to a logic one value. The sticky value can then be derived from the output of the combination logic. This provides a particularly efficient technique for determining the sticky value without awaiting the production of the final product in non-redundant form.

AI hardwareG06F 7/49963G06F 7/487G06F 7/49915G06F 7/49936

AI classification

AI hardware0.95
Machine learning0.00
Vision0.00
Planning0.00
Knowledge representation0.00
Speech0.00
Natural language0.00
Evolutionary computation0.00

Ownership

ARM LIMITED

assignment · 166000498

Assignors

LUTZ, DAVID RAYMOND, HINDS, CHRISTOPHER NEAL

On an employer assignment, the assignors are typically the inventors.

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