Patent US 7,685,458

Systems and methods for managing power consumption in an integrated circuit to reduce the rate of change of current (di/dt) in the integrated circuit. One embodiment comprises a system having multiple processor cores. A timing system provides each of the processor cores with a corresponding operating clock signal. The timing system uses variable delay elements to impart variable delays to the clock signals. A delay management unit determines the delays that should be used by the task processing units in executing their assigned tasks and provides this information to the variable delay elements to set the appropriate delays in each of these elements. The delay information is also provided to a task management unit, which assigns the tasks to specific processor cores based upon the delays selected by the delay management unit, so that consecutively fired processor cores are not adjacent to each other.