TRANSPARENT RETURN TO PARALLEL MODE BY TRAMPOLINE INSTRUCTION SUBSEQUENT TO INTERRUPT PROCESSING TO ACCOMMODATE SLAVE PROCESSOR NOT SUPPORTED BY OPERATING SYSTEM

A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables. A system includes a master processor having a first state, a slave processor having a second state, and a buffer memory. The system is operable to switch from a parallel mode to a serial mode responsive to an interrupt or exception and save the states to the buffer memory. Responsive to the interrupt or exception occurring in the slave processor, the system sets at least one variable in the first state to that of a variable in the second state. Responsive to the interrupt or exception occurring in the master processor, the system saves a first return address from the first state and the second state to the buffer memory and replaces the first return address with an address of a trampoline instruction. The trampoline instruction switches the system to the parallel mode of operation and reads the second state and the first return address from the buffer memory.