POWER MANAGEMENT ADAPTED TO COMPUTE AVERAGE LENGTH OF TIME THAT A PROCESSOR IS IDLE DURING EACH PROCESSING CYCLE FROM SYNCHRONIZATION SIGNALS

A SIMD processor architecture (2) for processing a stream of data vectors is provided, the architecture comprising a processor array (4) comprising a plurality of processors (PE(0), . . . , (PE(N)), each processor ((PE(0), . . . PE(N)) being adapted to process a data element in each vector, the operation of the processor array (4) being controlled by a local clock signal having a first frequency; a control processor (16) adapted to control the operation of the SIMD processor architecture (2) and generate signals to synchronize the operation of the processor array (4) with the stream of data vectors, the operation of the control processor (16) being controlled by a local clock signal having a second frequency; and power management means (30) for adjusting the frequencies of the local clock signals in response to the synchronization signals generated by the control processor (16), thereby minimizing the power consumption of the SIMD processor architecture (2).