MEMORY CONTROLLER WITH BANK SORTING AND SCHEDULING

In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank. An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.