FLASH ADC

An analog to digital converter (ADC) includes a resistance ladder including N resistances arranged in series. Connection nodes are arranged between adjacent ones of the N resistances and at each end of the resistance ladder. An input signal is received at a selected connection node of the connection nodes. N is an integer greater than one. A plurality of delay elements receive signals from corresponding ones of the connection nodes and apply predetermined delays to the signals to produce delayed signals. The predetermined delays are based on an electrical distance between the corresponding ones of the connection nodes and the selected connection node, respectively. A plurality of comparators include corresponding first input terminals that receive the delayed signals from respective ones of the plurality of delay elements.