SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DATA PROCESSOR HAVING A CLUSTERED ARCHITECTURE

Patent №

US 7,779,240

Granted

2010-08-17

Filed 2007

Owner

Lab

AI components

1

hardware

Assignment

None on record

Dataset

AIPD

2023_r1 edition

Application

11900978

There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address, (ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

AI hardwareG06F 9/30058G06F 9/3885

AI classification

AI hardware0.80
Vision0.09
Planning0.09
Evolutionary computation0.03
Knowledge representation0.00
Natural language0.00
Machine learning0.00
Speech0.00
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